Integrated circuits have become larger and more complex to provide additional functionality and/or improved performance. The task of designing these integrated circuits is also very complex and time consuming, involving synthesizing, analyzing and optimizing many circuit parameters. Because of this complexity, electronic design automation (EDA) systems have been developed to assist designers in developing integrated circuit designs at multitude levels of abstraction.
To ease the design of a complex integrated circuit, design tasks may be divided up into multiple functional blocks with a plurality of levels of hierarchy. However, dividing up an integrated circuit design into multiple blocks and hierarchical levels can complicate the evaluation of the overall circuit design. Moreover an integrated circuit design may be so large in size (e.g., 20-30 million gates), each partition may have numerous signal paths (e.g., hundreds of thousands of signal paths for data, address, control, and clock signals) and numerous input, output, or input/output ports (e.g., thousands of ports).
Timing budgets for signal paths are usually automatically generated in early design stages when the integrated circuit design may be incomplete or have errors so that generated timing budgets may require manual correction and analysis. The process of automatic timing budgeting usually generates much time budgeting data so that the quality of the generated timing budgets may be analyzed. However, this time budgeting data is usually represented by one or more simple text files that have large file sizes (e.g., gigabyte size), making it difficult to timely analyze. Moreover if a user changes one block constraint, it is often very difficult to propagate changes to other blocks of the integrated circuit design using text files.
Thus, there is a need for an apparatus, systems, and methods to better evaluate the quality of time budget results for hierarchical integrated circuit designs and readily make corrections thereto so that goals of an integrated circuit design may be timely met.